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Today I worked on designing the DTACK` logic systems. I currently am using discrete logic, chip enables, and end of conversion outputs to get a low to DTACK` when data is being transferred. My one concern is that the chip enables will give a DTACK` low when it shouldn't be low, in respect to transfers involving slower chips. If anyone knows how to deal with this, please assist me.
I also made a schematic of my anti-imaging/anti-aliasing filters today. They are 4 pole Bessel low pass filters, with a cutoff frequency around 17kHz. I hope to create a full schematic soon; this would help me, as my circuit is quickly running out of control and will soon become too confusing if it isn't dealt with soon.
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