Structured Computer Organization, by Tanenbaum
Chapter 2: Computer Systems Organization

• A digital computer consists of an interconnected system of
  processors, memories, and input/output devices.
• Processors: CPU is the "brain" of the computer
• Function is to execute programs stored in main memory by
  • fetching their instructions
  • examining them
  • executing them one after another
• The components are connected by a bus
• CPU composed of:
  • Control unit - fetches instructions from main memory and
    determines their type
  • Arithmetic logic unit - performs operations such as addition and
    Boolean AND needed to carry out the instructions
  • Small high speed memory used to store temporary results and
    certain control information
  • This memory is made up of a number of registers, each of which
    has a certain function
  • Registers can be read and written at high speed since they are
    internal to the CPU
  • Important registers are:
    • Program Counter (PC) - points to the next instruction to be
      fetched for execution
    • Instruction Register (IR) - holds the instruction currently
      being executed
• CPU Organization
  • Data Path:
    • Registers
    • ALU
    • several buses for connecting these pieces
  • The registers feed into two ALU input registers, A and B
  • These registers hold the ALU input while the ALU is computing
  • The ALU yeilds a result to the output register
  • The output register can be stored back into a register
  • Later, the output register can be written (stored) into memory
  • Instructions consist of two categories:
    • Register-memory - allow memory words to be fetched into registers
    • Register-register - fetch operands from the registers
  • Data path cycle: the process of running two operands through
    the ALU and storing the result
• Fetch-decode-execute cycle: The CPU executes each instruction in
  a series of small steps
  1. Fetch the next instruction from memory into the
     instruction register (IR)
  2. Change program counter (PC) to point to the following instruction
  3. Determine the type of instruction just fetched
  4. If the instruction uses a word in memory, determine where it is
  5. Fetch the word, if needed, into a CPU register
  6. Execute the instruction
  7. Go to step 1 to begin executing the following instruction
• The description of how the CPU works closely resembles a program:

    PC = starting address;  //Preliminary to Step 1
    while (run_bit) {
       instr = memory[PC];  //Step 1
       PC = PC + 1;         //Step 2
       instrType = getInstType(instr);  //Step 3
       dataLoc = findData(instr, instrType); //Step 4 (check)
       if (dataLoc >= 0) 
          data = memory[dataLoc];  //Step 5
       excute(instrType, data);   //Step 6
    }   //Step 7, begin the loop again
  

• The above program shows that software can imitate the function
  of a CPU.
  • A program need not be executed by a "hardware" CPU
  • Instead, a program can be carried out by having another program
    fetch, examine, and execute its instructions
  • This other program is called an interpreter
• An interpreter breaks down the instructions of its target machine
  into small steps
• A machine on which teh interpreter runs can be much simpler and
  less expensive than a hardware processor for the target machine
  would be
• Early 1950's - IBM introduces concept of architecture -
  • Support a single family of machines, all of which execute
    the same instructions
  • Compatability of lower generations of machines
  • A new family of computers would have one architecture but
    many different implementations that could all execute the same
    program.
  • Interpretation was the key to building lower-cost computers that
    could execute a large number of instructions.
• Motorola 68000 had a large interpreted instruction set, beats
  Zilog Z8000 chip which had an equally large instruction set, but
  without an interpreter.
• RISC vs CISC. In 1980, experiments with chips that did not use
  interpretation
• To compete, Intel began to employ RISC ideas in a CISC architecture
  • Starting with the 486, Intel CPUs contain a RISC core that
    executes the simplest (and most common) instructions in a single
    data path cycle (RISC)
  • Interpret the more complicated instructions in the usual CISC way
  • "hybrid" approach
• Design Principles for Modern computers
  • All common instructions are directly executed by hardware
    • Not interpreted by microinstructions
    • Eliminating a level of interpretation provides high speed
      for most instructions
    • For computers that implement CISC instruction sets:
      The more complex instructions can be broken into separate
      parts, which can then be executed as a sequence of
      microinstructions
  • Maximize the rate at which instructions are issued.
    Issue as many instructions per second as possible
  • Instructions should be easy to decode
  • Only loads and stores should reference memory
    • Require that operands for most instructions come from, and
      return to, registers
    • Access to memory can take a long time, and the delay is
      unpredictable
  • Provide plenty of registers
  • Instruction level parallism: Pipelining
    • Divide instruction execution into many parts, each one
      handled by a dedicated piece of hardware, all of which can
      run in parallel
    • Sample 5 stage pipeline:
      1. Stage 1: fetch instruction from memory, place in a buffer
         until needed
      2. Stage 2: decode the instruction, determine its type
         and what operands it needs
      3. Stage 3: locate and fetch the operands, either from
         from registers or from memory
      4. Stage 4: do the work of carrying out the instruction,
         running the operands through the data path
      5. Stage 5: write the result back to the proper register
    • Some math:
      • Suppose that the cycle time for the above pipeline
        machine is 2 nsec
      • Then it takes 10 nsec for an instruction to progress
        all the way through the 5-stage pipeline
      • With each instruction taking 10 nsec, it appears the
        machine can run at 100MIPS:
        1 instr/10 nsec = 1 instr/10*10^-9 seconds
        = 1 instr/10^-8 sec = 10^8 instr/sec
        = 100 * 10^6 instr/sec = 100 MIPS
      • But with every clock cycle (2 nsec) one instruction
        is completed, so the actual rate is 500 MIPS:
        1 instr/2 nsec = 1 instr/2*10^-9 seconds
        = .5 instr/10^-9 sec = 5 instr/10^-8 sec
        = 5 * 10^8 instr/sec
        = 500 * 10^6 instr/sec = 500 MIPS
    • Pipelining allows a trade-off between
      • latency - how long it takes to execute an instruction
      • and processor bandwidth - how many MIPS the CPU has
      • Formula: with a cycle time of T nsec and n stages in the
        pipeline
        • Latency is nT nsec
        • Bandwidth is 1000/T MIPS
        • In the above example
          Latency = nT = 5 stages * 2 nsec = 10 nsec
          Bandwidth = 1000/T = 1000/2nsec = 500 MIPS
      • Superscalar architectures - more than one pipeline,
        u and v pipelines
  • Processor level parallelism
    • array processor
    • vector processor
    • multi processors
    • multi computers
    • SISD, SIMD, MIMD